An ISFET, when immersed in an electrolyte such as blood, exhibits a change in the electrical conductivity on the semiconductor surface under the gate insulating film thereof. Notably, this change in electrical conductivity is the result of a change in the electrical potential at the boundary between the electrolyte and the insulating film. The level of ion activity in the electrolyte can be measured by making use of this change in the electrical conductivity.
The ISFET has to be electrically insulated in the electrolyte. In the Figure drawings, symbols D and S are used to denote drain and source regions, respectively. Conventionally, arrangements as shown in FIGS. 5 and 6 have been used for the purpose of electrically insulating ISFETs in electrolytes. More specifically, in the arrangement shown in FIG. 5, a silicon oxide film 2 and a silicon nitride film 3 are applied as coatings to the outer peripheral surface of the portion of a silicon substrate 1 of the ISFET immersed in the electrolyte. On the other hand, in the arrangement of FIG. 6, a ceramic substrate 4 is bonded to one side surface of the immersed portion of the silicon substrate 1 of the ISFET, while the opposing side surface is covered with a silicon oxide film 2 and a silicon nitride film 3. In addition, the entire area of the outer peripheral surface except the gate insulating film 5 is coated with an RTV rubber or an epoxy resin 6.
FIG. 7 also shows a known arrangement which employs a substrate 7 made of sapphire on which Si is made to grow. The entire surface of the silicon substrate 1 except the gate insulating film 5, is covered by a silicon oxide film 2 and a silicon nitride film 3.
These known ISFETs, however, suffer from the following disadvantages. Namely, the ISFET shown in FIG. 5 has insufficient dielectric strength because it is rather difficult to form insulating films 2, 3 of superior quality on the side surface of the element. In particular, the insulation tends to break down when the electrical potential of the electrolyte becomes positive with respect to the silicon substrate, with the result that the ISFET fails to function.
In case of the ISFET shown in FIG. 6, it is difficult to form a coating of the insulating resin 6 because the element is very small. In addition, there is a risk that the performance of the ISFET is rendered unstable due to invasion of the electrolyte in a minute gap which may be formed between the insulating resin 6 and the ceramic substrate due to insufficient bonding therebetween.
The ISFET of the type shown in FIG. 7 encounters difficulty in cutting into chips because the insulation on one side thereof is constituted by sapphire which is very hard.
In order to obviate these problems, Japanese Utility Model Publication No. 58-5245 proposes a structure of the type shown in FIG. 8. According to this proposal, an ISFET is formed having a P-type silicon substrate 1, which is surrounded at its three sides by an N-type diffusion layer 8 and a P-type diffusion layer 9, with the remainder side faced by a silicon oxide film 2 and a silicon nitride film 3. In this arrangement, an insulative layer is formed by making use of reverse dielectric strength of the PN junction formed by the P-type and N-type diffusion layers. According to this proposal, it is possible to obtain sufficient insulation between a small element and the electrolyte without requiring the outer configuration of the Si substrate to be processed. However, since the N-type diffusion layer and the P-type diffusion layer have to be formed in such a manner as to surround the silicon substrate, it is necessary to employ complex processes, such as embedding diffusion and epitaxial growth, with the result that the production process is rendered too complicated.